VHDL with-select error expecting "(", or an identifier or unary operator

Question

I am writing a 2bit 4 input multiplexer in VHDL based solely on a truth table. I am using the with-select statement Code . However I get the following error messages: Error messages on the last 4 lines. I cannot find any syntax errors and looking at other examples of with-select look exactly like mine. I am thinking I might have made a mistake with assigning vector values but I can't find the error. The software is Quartus Prime Lite.

Code:

LIBRARY ieee;
use ieee.std_logic_1164.all; 
    entity tut43mux IS 
        PORT(
        --sw: in Std_Logic_Vector(9 downto 0);
        --LEDR: out Std_Logic_Vector(9 downto 0));
        sw: in Std_Logic_Vector(0 to 9);
        LEDR: out Std_Logic_Vector(0 to 9));
        end tut43mux;

    architecture behavior of tut43mux is
        --signal s,u,v,w,x,t,y,m: Std_Logic_Vector(1 downto 0);
        signal s,u,v,w,x,m: Std_Logic_Vector(0 to 1);
        begin
            LEDR(0)<=m(0);LEDR(1)<=m(1);

            LEDR(2)<=sw(2);LEDR(3)<=sw(3);
            LEDR(4)<=sw(4);LEDR(5)<=sw(5);
            LEDR(6)<=sw(6);LEDR(7)<=sw(7);
            LEDR(8)<=sw(8);LEDR(9)<=sw(9);

            s(0)<=sw(0);s(1)<=sw(1);
            u(0)<=sw(2);u(1)<=sw(3);
            v(0)<=sw(4);v(1)<=sw(5);
            w(0)<=sw(6);w(1)<=sw(7);
            x(0)<=sw(8);x(1)<=sw(9);

            with s select m     
                    <= u when "00",
                    <= v when "01",
                    <= w when "10",
                    <= x when "11",
                    <= "00" when others;

        end architecture behavior;

Answer 1

you only need <= for the first assignement in the with.. select statement. The rest do not need it.

with s select
  m <= u when "00",
       v when "01",
       w when "10",
       x when "11",
    "00" when others;