Shift Register not working in Verilog HDL

Question

I'm trying to design a 64-bit Shift register in Verilog HDL but when I test the code with a testbench, all the bits are zeros. I don't know where I'm going wrong. Here is my code and the test bench result:

module ShiftRegister (shift_out, clk, shift_in, rst); //module ports
 parameter n = 64; //Parameter n declared to store 64
 input rst;
 input [n-1:0] shift_in; //64-bit input shift_in
 input clk; //Input clock
 output [n-1:0] shift_out; //64-bit output shift_out
 reg [n-1:0] ff; //64-bit flipflop
  assign shift_out = ff [n-1:0]; //give the output of the 64th bit
  //The operation of verilog: 
   always @ (posedge clk or posedge rst) //Always at the rising edge of the clock
   begin
     if (rst) begin
     ff <= 0;
   end else begin
     ff <= ff << 1;  //Shift bits to the left by 1
     ff[0] <= shift_in; //Take the input bits and give it to the first flipflop
   end
   end
 endmodule


 module ShiftRegister_tb; //Module shiftRegister_tb
  parameter n = 64; //Parameter n declared to store 64
  reg [n-1:0] shift_in; //64-bit register input shift_in
  reg clk, rst; //register clock
  wire [n-1:0] shift_out; //64-bit wire output shift_out
  ShiftRegister DUT(shift_out, clk, shift_in,rst); //Calling the module
   initial
   begin
     clk = 0; //clock = 0 initally
     rst = 1;
     shift_in = 64'd34645767785344; //Random decimal number to test the code 
     #100;
     rst = 0;
     #50_000 $finish;
   end   
  always #50 clk =~clk; //invert the clock input after 50ps
 endmodule //ShiftRegister testbench 

Answer 1

Here ff[0] <= shift_in;, you are trying to assign a 64-bit variable to 1-bit variable. Since you use a even number (64'd34645767785344) for shift_in in your testbench, its LSB is 0. Therefore, you keep inserting 0 to ff.

Make your shift_in input 1-bit and change your testbench such that you will give 1-bit at a time as input.