What does this Chisel exception mean: Caused by: chisel3.package$RebindingException: Attempted reassignment of binding to Reset

Question

I got the error chisel3.package$RebindingException: Attempted reassignment of binding to Reset(IO in unelaborated TLDebugModule) when attempting to change the module (TLDebugModule) from a regular Module to a RawModule. I'm not sure what this message is saying, can you help understand what it's saying so I can look for what I am doing wrong?

Here's the diff of my RTL:

     val io = IO(new Bundle {
       val debug_clock = Input(Clock())
       val debug_reset = Input(Reset())
+      val tl_clock = IO(Input(Clock()))
+      val tl_reset = IO(Input(Reset()))
+
       val ctrl = new DebugCtrlBundle(nComponents)
       val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO()))
       val apb_clock = p(ExportDebug).apb.option(Input(Clock()))

@@ -1780,11 +1789,11 @@ class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
       dmOuter.module.rf_reset := r
     }

-    dmInner.module.clock := io.debug_clock
-    dmInner.module.reset := io.debug_reset
     dmInner.module.rf_reset := io.debug_reset
-    dmInner.module.io.tlClock := clock
-    dmInner.module.io.tlReset := reset
+    dmInner.module.io.debug_clock := io.debug_clock
+    dmInner.module.io.debug_reset := io.debug_reset
+    dmInner.module.io.tl_clock := io.tl_clock
+    dmInner.module.io.tl_reset := io.tl_reset

+++ b/src/main/scala/devices/debug/Periphery.scala
@@ -103,6 +103,8 @@ trait HasPeripheryDebugModuleImp extends LazyModuleImp {
   val psd = IO(new PSDIO)

   val resetctrl = outer.debugOpt.map { outerdebug =>
+    outerdebug.module.io.tl_reset := reset
+    outerdebug.module.io.tl_clock := clock
     val resetctrl = IO(new ResetCtrlIO(outerdebug.dmOuter.dmOuter.intnode.edges.out.size))
     outerdebug.module.io.hartIsInReset := resetctrl.hartIsInReset

Answer 1

I think your problem is that you have nested calls to IO at try removing the inner IO calls.