Generated begin-end blocks must be named

Question

I am compiling an SNN simulator named "ODIN" in Xilinx. for Generate block I get this error but I think there is nothing wrong with this block. Can you help me with this?

'''
genvar i;
generate
    for (i=0; i<8; i=i+1) begin
    
        sdsp_update #(
            .WIDTH(3)
        ) sdsp_update_gen (
            // Inputs
                // General
            .SYN_PRE(CTRL_PRE_EN[i] & (SPI_UPDATE_UNMAPPED_SYN | SYNARRAY_RDATA[(i<<2)+3])),
            .SYN_BIST_REF(CTRL_BIST_REF),
                // From neuron
            .V_UP(NEUR_V_UP_int[i]),
            .V_DOWN(NEUR_V_DOWN_int[i]),    
                // From SRAM
            .WSYN_CURR(SYNARRAY_RDATA[(i<<2)+3:(i<<2)]),
            
            // Output
            .WSYN_NEW(SYNARRAY_WDATA_int[(i<<2)+3:(i<<2)])
        );
    end
endgenerate

I get these errors:

Generated begin-end blocks must be named

Illegal redeclaration of ''

Answer 1

Some compilers wants to have a name when generating logic. This name is taken from the name of the begin-end block. Try this:

'''
genvar i;
generate
    for (i=0; i<8; i=i+1) 
    begin : sdsp_gen // <<< Name for begin/end block 

        sdsp_update #(
            .WIDTH(3)
        ) sdsp_update_gen (
            // Inputs
                // General
            .SYN_PRE(CTRL_PRE_EN[i] & (SPI_UPDATE_UNMAPPED_SYN | SYNARRAY_RDATA[(i<<2)+3])),
            .SYN_BIST_REF(CTRL_BIST_REF),
                // From neuron
            .V_UP(NEUR_V_UP_int[i]),
            .V_DOWN(NEUR_V_DOWN_int[i]),    
                // From SRAM
            .WSYN_CURR(SYNARRAY_RDATA[(i<<2)+3:(i<<2)]),

            // Output
            .WSYN_NEW(SYNARRAY_WDATA_int[(i<<2)+3:(i<<2)])
        );
    end
endgenerate