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verilogsystem-verilog

What's the difference when time delay specified in LHS or RHS?

a = #5 b;
#5 a = b;

Is there any difference between above 2 statements?

Solution

  • The # on the RHS is known as an intra-assignment delay. Read about the distinction in the IEEE Std (1800-2009), section 9.4.5 "Intra-assignment timing controls".

    An intra-assignment delay or event control shall delay the assignment of the new value to the left-hand side, but the right-hand expression shall be evaluated before the delay, instead of after the delay.

    Run a simulation with both statements to see what difference (if any) you observe. Use $monitor and $time.