corresponding expression between Verilog and VHDL

In source code of rtl, which is written in Verilog, there is a variable

event start_simulation;

I would like to perform -> start_simulation; from a file of test bench, which is written in VHDL.

What is a corresponding sentence in VHDL?

Solution

There is no such thing as an event variable in VHDL.

In VHDL, an event is a change in value of a signal (updating the signal with the value it already has does not trigger an event).

Events are generally used in sensitivity lists (the list of signals which do activate a process):

process(signal_a)
begin
  -- do some stuff when the value of signal a changes
end process;

If something should only happen on a event and a condition, it is possible to add conditions:

process(signal_a, signal_b)
begin
  if signal_a'event and signal_a = '1' then
    -- run only on rising edge of signal a
  else
    -- will run on signal a's falling edge or signal b event
  end if;
end process;

Depending on how you wish to implement your testbench there are many ways to handle the start of the simulation with and without events.