I work on a high-level simulator written in C++ for some hardware that is written in System Verilog.
The System Verilog code includes a number of functions that contain only logic (that is, nothing time-consuming, no flip-flops). I want to reuse this code in my C++ simulator.
Is there any way to reuse these functions in C++ (or C, which is easily linked into C++) by way of:
Typically this kind of integration is done in the other direction, meaning calling C/C++ routines from Verilog. Of course, that only makes sense for verification components, obviously that can't be synthesized. The most likely environment to do what you want is a SystemC/Verilog cosimulation, but that implies both the use of a Verilog simulator (which you explicitly don't want), and a C model using SystemC.
Simulators seeking high performance often generate C or native code. I'm not aware of any way to extract specific functions from the generated code in VCS (the simulator I'm most familiar with), but it might be possible to do so with one of the open source simulators. Any commercial (i.e., licensed) simulator is unlikely to support generating code that you can run without a license. I'm not sure if your desire to use the Verilog functions independent of the simulator is driven by licensing, runtime overhead, tool installation burden, or something else entirely.
I'm assuming you don't maintain the SystemVerilog routines, so it may not be possible to change the way they're implemented. However, if it is possible, one common strategy when functionality is needed both in C and in Verilog is to write code generators that can transform a single definition into C and Verilog implementations.
Another more esoteric possibility is SystemC synthesis. It is relatively new and I don't have experience with it, but if you have access to the tools and they work for your functions, it would allow you to reuse a C implementation for C models, hardware simulation, and synthesis.