How to determine that synthesis is done in Quartus?

My design is done in Verilog and I need to select specific solution for synthesis in Altera Quartus II. I know that many tools have predefined macros, for example Icarus Verilog has built-in macro __ICARUS__. But I was unable to find such macro for Quartus. Is it a simple way to detect it?

Solution

Yes, Altera/Intel Quartus II Integrated Synthesis (QIS) has predefined macro that is used extensively by QIS in their demos and IPs. This macro is actually undocumented but it works in all known versions of Quartus II. Here is it:

`ifdef ALTERA_RESERVED_QIS
  // The code that is used for Quartus Synthesis
`else
  // The code that is used for other software
`endif

Can't see anything when accessing RAM contents in simulation
Cannot load/store data from/in SRAM: read data is unknown
Verilog to GDSII compiler (open-source)
Output not updated as expected
How to add all, except one file in iverilog command line instruction from a folder?
Verilog module not being called
Static vs. automatic tasks
Xilinx Vivado 2023 IP block design issue: Unable to connect output of RTL module to AXI GPIO output that is connected to LED
Why do I get a syntax error using the ternary operator with function calls?
Constraint to randomize such a way that consecutive 2 bits are set to 1, other bits are 0 for 16-bit variable
Verilog port mapping when a gate netlist module's vector ports instatantiated inside an rtl module have been split into each bit by P&R tool
What is the best practice to handle invalid or illegal combinations of inputs in a verilog module?
Verilog slice direction differs from VHDL
Systemverilog/Verilog VCP2000 “Syntax error. Unexpected token: class[_IDENTIFIER].”
How to compile and run a single verilog file with Questa?
Use loop to access generated modules
Parity checker in verilog only calculates a result once
How to check signal drive strength?
Variable scope verilog: Why does $display inside the task print the global variable sig and not the local variable sig that was declared within task
Array of wire OR-reduction is wrong
Random constraints on array of structure elements
$dumpfile and $dumpvars not working in vscode. Error in terminal says requires SystemVerilog
How to select bits in expression?
D-type Flip Flop - Behavioral vs Gate-Level Modeling in Verilog, Timing of state transitions
What's the best way to tell if a bus contains a single x in Verilog?
Not getting the full Timing Report in Synthesis Report
Reducing OR not working as expected when bit slicing in a loop
SystemVerilog testbench: Making an array of logic with run-time determined width
Modules compiling to 0 gates
Why does blocking vs. non-blocking matter in this Verilog snippet?