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chiselrocket-chip

How to keep val names under withClock() or withClockAndReset() scopes

Val names under withClock() & withClockAndReset() scopes tend to lose their coded names in the generated Verilog file.

So far in order to maintain to original names I used suggestName() function to force the original name.

However I wonder if there is a smarter way do it ? is there a way to force all vals to keep their names without adding suggestName() to each val declaration ?

Solution

  • As Kamyar mentioned in his comment, you should use the @chiselName macro

    import chisel3._
import chisel3.experimental.chiselName

@chiselName
class MyModule extends Module {
  ...
  withClock(otherClock) {
    val importantReg = Reg(...) // <- this will now get a name
  }
}

    The way @chiselName works is it will automatically add a .suggestName to each val.