Response signal when performing a store into the L1 Dcache of Rocket Chip Core

Question

If I perform a store into the L1 Dcache does the Rocket Chip core produce a resp valid signal or is that only for a load signal? Cos for a load signal you are requesting something and you get something in response whereas for the store you just need to check if the memory interface is ready and send out the signal. (I am talking about the io.mem.resp field)

Answer 1

I figured out the answer. In short while performing a store operation it is just a ready-valid interface.