Can't poke MixedVec

Question

I declared a MixedVec in my Module interface:

class WbInterconOneMaster(val awbm: WbMaster,
                          val awbs: Seq[WbSlave]) extends Module {
    val io = IO(new Bundle{
      val wbm = Flipped(new WbMaster(awbm.dwidth, awbm.awidth))
      val wbs = MixedVec(awbs.map{i => Flipped(new WbSlave(i.dwidth, i.awidth, i.iname))})
    })

That compile correctly and Verilog is correctly generated. But I can't poke values on signal like it :

  for(wbs <- dut.io.wbs) {
    poke(wbs.ack_o, 0)
  }

Got this error at execution time (verilator backend):

[info]   java.util.NoSuchElementException: head of empty list
[info]   at scala.collection.immutable.Nil$.head(List.scala:420)
[info]   at scala.collection.immutable.Nil$.head(List.scala:417)
[info]   at scala.collection.mutable.Stack.top(Stack.scala:132)
[info]   at chisel3.internal.naming.NamingStack.pop_return_context(Namer.scala:133)
[info]   at chisel3.util.MixedVec.length(MixedVec.scala:81)
[info]   at scala.collection.IndexedSeqLike$class.iterator(IndexedSeqLike.scala:90)
[info]   at chisel3.util.MixedVec.iterator(MixedVec.scala:81)
[info]   at scala.collection.IterableLike$class.foreach(IterableLike.scala:72)
[info]   at chisel3.util.MixedVec.foreach(MixedVec.scala:81)
[info]   at wbplumbing.TestWbInterconDualSlave.<init>(testwbplumbing.scala:61)

Note that the question was already asked on github project with the chisel version 3.1.6 but it's marked as closed. I'm using 3.1.8 version and it seems to be broken yet.

[edit]

I upgraded my project with chisel 3.2.0 and iotester 1.3.0 :

libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.2.0"
libraryDependencies += "edu.berkeley.cs" %% "chisel-iotesters" % "1.3.0"

And I still have an error when I uncomment the line :

  for(wbs <- dut.io.wbs) {
    poke(wbs.ack_o, 0)
  }

(if I left these lines commented, that works)

But the stack trace is different :

[info] - should read and write wishbone value on two slaves *** FAILED ***
[info]   chisel3.internal.ChiselException: Error: Not in a RawModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox.
[info]   at chisel3.internal.throwException$.apply(Error.scala:42)
[info]   at chisel3.internal.Builder$.referenceUserModule(Builder.scala:287)
[info]   at chisel3.Data.connect(Data.scala:384)
[info]   at chisel3.Data.$colon$eq(Data.scala:475)
[info]   at wbplumbing.TestWbInterconDualSlave$$anonfun$15.apply(testwbplumbing.scala:63)
[info]   at wbplumbing.TestWbInterconDualSlave$$anonfun$15.apply(testwbplumbing.scala:62)
[info]   at scala.collection.Iterator$class.foreach(Iterator.scala:742)
[info]   at scala.collection.AbstractIterator.foreach(Iterator.scala:1194)
[info]   at scala.collection.IterableLike$class.foreach(IterableLike.scala:72)
[info]   at chisel3.util.MixedVec.foreach(MixedVec.scala:88)
[info]   ...

Answer 1

I am not sure what is going on but I was able to reproduce your error in the current chisel3 release, but the same code seems to run properly under the chisel 3.2 release candidate snapshot. Is it possible for you to try your code there. Hopefully it will work better. The problem does not appear to be directly in MixedVec but must be in underlying code.

I must say that you need to be especially careful when using MixedVec, it is not indexable by a hardware index, so all references to its elements must be referenced from constant Scala ints at elaboration time.