vhdl delay line implementation attribute

Question

A newbie question related to vhdl attributes. In this implementation of 128-deep 8-bit delay line on LUT RAM, attribute part confuses me.

entity srl_128_lutram is 
  generic ( 
    LENGTH     : integer := 128; 
    ADDRWIDTH : integer := 7; 
    WIDTH      : integer := 8); 
  port ( 
    CLK        : in  std_logic; 
    SHIFT_IN  : in  std_logic_vector(WIDTH-1 downto 0); 
    SHIFT_OUT : out std_logic_vector(WIDTH-1 downto 0)); 
end srl_128_lutram; 

architecture behavioral of srl_128_lutram is 

  signal CNTR : std_logic_vector(ADDRWIDTH-1 downto 0); 
  type ram_type is array (0 to LENGTH-2) of std_logic_vector(WIDTH-1 downto 0); 
  signal RAM : ram_type := (others => (others => ’0’)); 

  attribute ram_style : string; 
  attribute ram_style of RAM : signal is "distributed"; 

begin 

  counter : process (CLK) 
  begin 
    if CLK’event and CLK = ’1’ then 
       if CNTR = conv_std_logic_vector(LENGTH-2, ADDRWIDTH)  then 
         CNTR <= (others => ’0’); 
       else 
         CNTR <= CNTR + ’1’; 
       end if; 
    end if; 
  end process counter; 

  memory : process (CLK) 
  begin 
    if CLK’event and CLK = ’1’ then 
       RAM(conv_integer(CNTR)) <= SHIFT_IN; 
       SHIFT_OUT                 <= RAM(conv_integer(CNTR)); 
    end if; 
  end process memory; 

end behavioral;

My question is what purpose of attributes are here ? What would happen without these two lines ?

Answer 1

EDIT :
Attributes are used to give some directives to synthetizer. The attribute syntax is a bit confusing but the meaning of your line is the following : For my signal RAM use the attribute ram_style with the value distributed. The attribute will never be used later in the code, it has already given his informations.

Note : attributes are differents from a synthetizer to another.

OLD :
The attribute RAM_STYLE gives to the synthetizer the type of physical cells use to implement your RAM.

In your case it will choose LUT rams. So it will consume some LUT rams of your total LUT ram ressources in your FPGA. You can also to use block RAM.

If you don't use this attribute, synthetizer will choose by itself between these 2 cells (probably with ressource and performance considerations).

Sources : https://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_3/ug901-vivado-synthesis.pdf (page 36)