Isim not running

I'm trying to run a full adder testbench. When i try to run the isim simulator it says "Running: Convert Schematics to HDL" then "No process Running". It doesn't even open the isim window.

I tried copying the schematics and the testbench in an other project but didn't do anything

Is there a place where i can upload my schematics and my testbench so someone could review it?

Solution

If you're using Windows 10, navigate to the following directory:

installation directory \Xilinx\14.x\ISE_DS\ISE\gnu\MinGW\5.0.0\nt\libexec\gcc\mingw32\3.4.2\collect2.exe

Locate the file named collect2.exe in this directory. Cut this file and paste it into a safe location as a backup. Keep it there until you're certain that everything is working as expected.

If did not work take a look at this link.

Is CRC Calculation Faster on Xilinx Alveo U280 FPGA Using a Custom Algorithm or a Lookup Table?
How to implement pipelined floating point accumulation in II=1 in Vitis/Vivado HLS?
Timing simulation in Vivado giving an error
Is it possible to tie ports high always high outside of top module?
How to fix [Common 17-1293] error in Xilinx Vivado?
How to initialize contents of inferred Block RAM (BRAM) in Verilog
Implementing hardware that divides an 8 bit number by 3 (11) in binary
Can SYSCLK be included in FPGA Xilinx vivado testbenches?
Isim not running
how to add python in xilinx vitis
Timing closure problems in FIFO
Xilinx Vivado schematic for if else statements
difference between Xilinx solarflare scaleout onlod, solarflare onload, and solarflare TCPDirect?
Inferring a True Dual Port RAM (Xilinx and Intel compatible) in Verilog
'case item is unreachable' in Vivado synthesis process
Why does the Inferred Latch error occur during the synthesis process?
What is the granularity of the AXI-ACE protocol?
Restricting Verilog parameters
Vitis HLS Pointer to Pointer is not supported for variable when initializing struct array
Vitis PetaLinux build cant fetch required files while building an application project
Address of a struct used to set MSI Base address, how does it work? (in Xilinx PCIe RC driver)
How To Convert .bit file to .bin
of_node_name_eq for device tree node label
using xilinx cores in modelsim via .do file
Add hwspinlock Linux Driver to Petalinux project
How to use XADC's GPIO on Xilinx KC705 FPGA
Need help in converting verilog module without input & output ports into synthesizable. Because module without input/output ports is not synthesizable
Windows driver API that enables multi-word read/write
question regarding limitations on using c instead of c++ on vitis hls
Linux Kernel Boot Error: reserving fdt memory region failed