Declare a port in Verilog where some bits are inputs and some are outputs

Question

In verilog for Cyclone 3 I want to declare a port where some pins are inputs and some are outputs, in many examples in web i see that a port is defined like

input wire [0:10]p;

but what to do if i need bit0 being an input of the IC, while others be an output. Tried like this and some other different variants, but every time i get errors from the compiler. Notice that IO[1] unused in code but present in "Assignment editor".

module main(
      tx,
      rx,
      IO[0],
      IO[2]
     );
output wire tx;
input wire rx;
input wire IO[0];
output wire IO[2];

assign IO[2] = rx;
assign tx = IO[0];

endmodule

Answer 1

You can use a port_expression. This separates the name of the port from the signals (or expression of signals) connected to the port. You might recognize this syntax when creating a module instance, but it has always been available for a module declaration as well in Verilog

module m(input .rx(a[0]), output .tx(a[1]));

  wire [1:0] a;
endmodule

module top;
  wire  a,b;  
  m m1(.rx(a),.tx(b));
endmodule