How to include vhdl modules to systemverilog file

I am trying to use two vhdl module in my systemverilog project in vivado. ( which are in the same project )

I have tried using include keyword at the beginning, which gave me no errors, but fails on synthesis , here is the error

[Synth 8-2715] syntax error near -- ["C:/Users/Batuhan/Desktop/fpga_VHDL_uart/Sonar_FPGA-master/src/MCU_UART_RX.vhd":1]

The line it shows is the first line of vhdl file which is just

-----------------------------------------------------------------------------

So I was wondering what is the proper way to include other modules

Solution

Simply instantiate them. Based on your error message I assume that you want to add MCU_UART_RX module to your testbench. So if you have a module Foo

entity Foo is
    Port ( Clk     : in STD_LOGIC;
           DataIn  : in STD_LOGIC;
           DataOut : out STD_LOGIC
           );
end Foo;

you can add this module to your System Verilog testbench by writing

bit SimulationClock;
bit SimulationDataIn;
bit SimulationDataOut;

Foo DUT(
    .Clk(SimulationClock),
    .DataIn(SimulationDataIn),
    .DataOut(SimulationDataOut)
);

Finally it look like this