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Is there a way to monitor the state of an internal signal with a University Program VWF in Quartus 13.1?

I have a VHDL finite statemachine. I created a internal TYPE akin to TYPE t_SM_Main IS (s_Idle, s_Start, s_TX1, s_TX0, s_Cleanup); I have also created a University Program VWF inside Quartus for the simulated response of my VHDL code.

Is it possible to have a signal that is defined inside the ARCHITECTURE be visible to the simulator without it being exported using the ENTITY PORT map? (which would also pose a problem because the TYPE definition needs to precede the PORT definition.)

Another way of phrasing it is that I'm wondering if there is a way to see the ENTITY not as a black box but as a white box.

I'm using Quartus II 64-bit 13.1 without any newer revisions of VHDL enabled.

update Seeing as variable is a better option as per the "’two-process’ design method". Is it possible to get the state of a variable inside a University Program VWF?

Solution

  • In a Simulation Waveform Editor select:

    1. Edit > Insert Node or Bus

    Insert Node or Bus

    1. Node Finder...

    Node finder

    1. in a new window that popęd up, change Filter to Design Entry (all names) (default: Pins: all)

    Filter

    1. list signals and choose those that you want to analyze.

    Pictures taken from Quartus II Tutorial