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vhdlverilog

VHDL equivalent to Verilog "10'h234"

I just need to know how to translate constant values from Verilog to VHDL. I wonder if I could still indicate the range and if it is hex, oct, binary, etc., just like in Verilog: 14'h1 -> I do not want to type anything like X"00000000000001" Thanks!

Solution

  • The answer depends on what VHDL standard you use.

    Before VHDL 2008, hex constants could only be directly expressed when the number of binary digits was a multiple of 4 (the length of an hex nibble).

    x"0001" is a 16-bit constant.

    With VHDL 2008, you can specify the bit length of the constant:

    x"0001" is still a 16-bit constant, whereas 14x"0001" is what you want: a 14 bit constant.

    If you are working with an earlier standard, you must work around this limitation like this:

    std_logic_vector(resize("1", 14)) or (0 => '1', others => '0')