I understand that Chisel is a HDL/HCL language to overcome some of Verilog/SystemVerilog restrictions by using higher abstraction level. And it is open source as well.
It might be a bit naive and presumptuous, but still I would like to ask.
My question is that why do so many similar efforts are working in parallel, e.g. Blusspec, spinalHDL, Pyha etc?
I mean, is there any reason why the development community may not choose one of these and concentrate efforts on stabilizing or enhancing one of these.
That's exactly what is happening now, it just takes a while to choose. Although the past does not show that the best technology wins, let us hope it does this time.