How will this loop work in SystemVerilog language?

Question

How will this loop work in SystemVerilog language ?

for(bit [2:0] i = 0; i < 4; i++)

What will be the values of i after each iteration provided i is 3 bit wire ?

Answer 1

bit [2:0] i;

As i is 3-bit value, it can take values from 0-7.

so i will get values 0,1,2,3