As I read from Chisel wiki, it is possible to declare several clock domain in a single module.
But if we need to read/write a signal through two different clock domains it's important to manage metastability (with dual d-latch, asynchronous fifo, ...).
If we don't manage it, it's a design error. Is there a way to ask chisel checking wrong clock domain crossing in design ?
Not at the moment. This is a needed, but as of yet unimplemented feature.