ModelSim compile successfully but i have wrong declaration in my code

Question

i'm beginner in modelSim and verilog

modelsim doesn't care about my name declaration and every name for Half_Adder module compile successfully
in section below i have Half_ that is not correct( because my module name is Half_Adder)but modelsim compile it with no errors

module Half_Adder(input a,b,output  s,c );
xor (s,a,b);
and(c,a,b);
endmodule
module Full_Adder(input a,b,c,output sum,carry);
wire sum1,carry1,carry2;
Half_  m1(a,b,sum1,carry1);
Half_Adder m2(sum1,c,sum,carry2);
or(carry,carry1,carry2);
endmodule

all above code is in one .v file i don't know it's correct or not

i tested above code in jdoodle online verilog compiler and it has error in name declaration : jdoodle.v:8: error: Unknown module type: Half_

but it's true in modelsim!

Answer 1

When you run on jdoodle, you are trying to compile and elaborate your code. It will be the elaboration step that is failing (because there is no Half_ module).

When you type vlog on Modelsim, you are just compiling, not elaborating your code. When you try to elaborate your code, you get an error in Modelsim:

vsim Full_adder

** Error: Half_Adder.v(7): Module 'Half_' is not defined.

Compiling Verilog is similar to compiling C or other languages. Each module is compiled separately. Elaborating is the final stage where all the modules are attempted to be linked together (and elaboration is somewhat analogous to linking in C and other languages). So, when any simulator tries to elaborate your code, you get an error because there is no Half_ module.