How can I fix assigning more than one value error in verilog?

Following is an attempt to study verilog hierarchical design. This is the circuit I am implementing:

Top Level module for the circuit is:

 module D_Filiflop_Hierarchal_top_level (clock, reset, i_d, q);

    input clock;
    input reset;
    input i_d;
    output [1:0] q;


    D_Flipflop u0 (.clk(clock), .rst(reset), .q(q[0]), .d(i_d));
    D_Flipflop u1 (.clk(clock), .rst(reset), .q(q[1]), .d(q[0]));

endmodule

And following is the D flip-flop module defined:

module D_Flipflop(clk,rst, d, q);
input clk;
input rst;
output d;
output reg q;

always @ (posedge clk or posedge rst) begin

    if (rst) begin
    q <= 1'b0;
    end

    else begin
    q <= d;
    end

end 

endmodule

But, this is the error message the console is showing:

Error (12014): Net "q[0]", which fans out to "q[0]", cannot be assigned more than one value
    Error (12015): Net is fed by "D_Flipflop:u0|q"
    Error (12015): Net is fed by "D_Flipflop:u1|d"

How can I fix this error?

Solution

Change output to input for d:

module D_Flipflop(clk,rst, d, q);
input clk;
input rst;
input d;
output reg q;