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verilogsystem-verilog

inputs without type in system verilog

I've encountered in an example for a system verilog code decleration of inputs and outputs for a module without stating their type, e.g logic, wire...

module mat_to_stream (
  input [2:0] [2:0] [2:0] a,b,
  input newdata,
  input rst, clk,
  output [2:0] [7:0] A_out, B_out);
  ...rest of code...

What is the diffrence between stating logic and not stating any type?

Solution

  • There is no difference between stating logic and not stating any type.

    input newdata,

    is equivalent to

    input logic newdata,

    The SystemVerilog IEEE Std (1800-2009) describes this in section: "23.2.2.3 Rules for determining port kind, data type and direction".