How should I implement the cascade of classifiers in Viola-Jones algorithm on FPGA?

I am trying to implement the Viola-Jones algorithm on FPGA. I am not sure what I should do about the cascade of classifiers. How should I implement it on the FPGA?

Solution

Check out this paper, seems exactly what you're looking for. You'll need a handle on VHDL or some hardware-description-language as well as some sort of breakout board like the Altera they are using.

Project Files and Source Code

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