Search code examples
hdlintel-fpga

AHDL dff resets to it default value


I'm doing variable frequency clock on AHDL. Algoritm is: one counter (trigger) counts from 0 to x, and when it reaches x - we have pulse. I have another trigger which is used to store that X. Also I have two inputs plus and minus which are used to change frequency (increase or decrease X value).

And I have following code:

constant maximum = 9;
constant minimum = 1;
constant default = 5;
subdesign generator(
    plus, minus, clk: input;
    pulse, level[3..0], curr_val[3..0]: output;
)

variable
    level[3..0]: dff;
    curr_val[3..0]: dff;

begin
    defaults
        level[].d = default; % load 5 as default X value %
    end defaults;

    level[].clk = clk;
    curr_val[].clk = clk;

    pulse = (curr_val[] == level[]); % if main counter reached X - send one pulsation %

    % main counter %    
    if curr_val[] < level[] then
        curr_val[] = curr_val[] + 1;
    elsif curr_val[] == level[] then
        curr_val[] = 0;
    end if;

    % buttons %
    if plus then
        if (level[].q > minimum) then % if X == maximum ignore button %
            level[].d = level[].q - 1;
        end if;
    end if;

    if minus then
        if (level[].q < maximum) then
            level[].d = level[].q + 1;
        end if;
    end if;
end;

The problem is - after one tick when I change X (level[]) value - it goes back to default value. Am I missing something?

Syntax highlighting is wrong since wrong tag. % text % is commentary.

enter image description here


Solution

  • Found the problem. The defaults block works everytime if value was not set. So, if you want to store same value you should set it at every time.