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chiselrocket-chip

How to iterate through similar registers definition in Chisel (regmap)

I have some similar register definition, and I want to write under the regmap construct. My code currently looks like this:

val regs = RegInit(Vec(Seq.fill(5)(0.U(32.W))))

regmap (
...
0x30 -> Seq(RegField(32,regs(0),RegFieldDesc("reg0",""),
0x34 -> Seq(RegField(32,regs(1),RegFieldDesc("reg1",""),
0x38 -> Seq(RegField(32,regs(2),RegFieldDesc("reg2",""),
0x3C -> Seq(RegField(32,regs(3),RegFieldDesc("reg3",""),
0x40 -> Seq(RegField(32,regs(4),RegFieldDesc("reg4",""),
...

)

My question, is there a way to write the above in more concise way using one of the Scala Iterators? Another requirement I have is that I still need to be able to add register before and after this iterator (3 dots lines).

I believe ,using iterators is good against copy/paste mistakes and looks better.
Thanks in advance for any help.

Solution

  • I think the pattern for this would probably be something like

    val regs = RegInit(Vec(Seq.fill(5)(0.U(32.W))))

val tuples = regs.zipWithIndex.map { case (reg, i) =>
  (0x30 + (i * 4)) -> Seq(RegField(32,regs,RegFieldDesc(s"reg$i","")))
}
regmap(tuples :_*)

    The only bit of magic there is the :_* which converts a sequence into a list of parameters.You don't need the multiple steps that I used either, I just wanted to make it easy to see what is going on.