I have error in `define on the Verilog with for

Question

...
'define ZERO_INIT2D(VECT,SD_WIDTH) for(integer i=0;i<(SD_WIDTH);i=i+1) (VECT)[i]=0;
...`

...
reg [31:0] rrr [7:0];
...
always @(negedge clk)
begin
        ZERO_INIT2D(rrr,8)
        //for(integer i=0;i<8;i=i+1) rrr[i]=0;// if using it. All works fine
        Buffer_reg = 111;
        Start_addr = 0;
        Counter=0;
...

I want to use exactly define! My define has nothing to do with the register "Buffer_reg". Why am I getting the following error?

ERROR:HDLCompiler:806 - "MEMORY_m.v" Line 170: Syntax error near "Buffer_reg".
ERROR:ProjectMgmt - 1 error(s) found while parsing design hierarchy.

Answer 1

I made such changes and everything was synthesized normally: ...

... 'define ZERO_INIT2D(VECT,SD_WIDTH) for(integer i=0;i<SD_WIDTH;i=i+1) VECT[i]=0; ...

I do not know why but

(VECT) -> VECT

(SD_WIDTH) -> SD_WIDTH

and it helped, but this also violates the syntax of defines, well, it works.