Error with localparam inside "for" loop on Verilog

Question

parameter N = 4, FOO = { N { 4'd1 } };
//And then in the generate loop
genvar i;
for( i = 0; i < N; i = i + 1 )
    begin : gen_loop
       localparam THIS_FOO = FOO[ i * 4 +: 4 ];
   end
wire [1:0] rr = THIS_FOO[1:0];
wire [1:0] rt = THIS_FOO[3:2];

I get this error but did not understand why?:

Line 344: <THIS_FOO> is not declared. 
Line 345: <THIS_FOO> is not declared.
Module <TCL_vec> ignored due to previous errors.

Please tell me where I was wrong?

Answer 1

Your localparam is declared inside begin:gen_loop..end scope. Moreover your generate for loop created multiple versions of the block, with names

gen_loop[0]
gen_loop[1]
...

So you have multiple versions of the THIS_FOO as well.The way to access them is to use a cross-reference notation.

wire [1:0] rr = gen_loop[0].THIS_FOO[1:0];
wire [1:0] rt = gen_loop[1].THIS_FOO[3:2];
...

and yes, you have to know which iteration of the loop to access.

So, in your case it complained because you do not have THIS_FOO declared in the scope you wanted to access it.