I am not sure I understand how to use the getVerilog function from: https://github.com/freechipsproject/chisel-bootcamp/blob/master/2.1_first_module.ipynb
[error] passthrough_test.scala:18:11: not found: value getVerilog
[error] println(getVerilog(new PassThrough(10)))
[error] ^
[error] one error found
[error] (Test / compileIncremental) Compilation failed
[error] Total time: 1 s, completed Nov 21, 2018 1:53:02 PM
I did import chisel3._ but that does not seem to be enough.
The getVerilog method is defined only in the Bootcamp. There's an equivalent method for Chisel versions prior to Chisel 3.2.0 called Driver.emitVerilog. For Chisel versions after 3.2.0, the correct method is (new chisel3.stage.ChiselStage).emitVerilog:
import chisel3._
import chisel3.stage.ChiselStage
class Foo extends Module {
val io = IO(new Bundle {})
printf("I'm a foo")
}
/* For Chisel versions <3.2.0 use the following: */
Driver.emitVerilog(new Foo)
/* For Chisel >=3.2.0 use the following: */
(new ChiselStage).emitVerilog(new Foo)
As an additional reference, the specific implementation of getVerilog in the Chisel Bootcamp is here. This looks almost identical to what Driver.emitVerilog is doing here. There was a similar, but slightly different question about generating Verilog that was brought up in a different SO question.
Usually if you're wondering if some API exists, it can be useful to search through the Chisel3 API reference. E.g., you can consult the documentation for ChiselStage for methods related to compiling Chisel to FIRRTL IR or Verilog: ChiselStage API.
For more control over Verilog generation, you'll want to use the ChiselStage class' method execute(args: Array[String], annotations: AnnotationSeq) if using Chisel >=3.2.0. Earlier versions of Chisel should use the Driver object's method Driver.execute(args: Array[String], dut: () => RawModule).
Note: ChiselStage.emitVerilog does allow you pass command line arguments and annotations to the Chisel compiler for more control over the generated FIRRTL IR or Verilog.