What is the meaning of := and := operators?

I see some examples in the RocketChip, but could not find info in the API reference

  masterNode :=* tlOtherMastersNode
  DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode }

Solution

These are not Chisel operators. Instead, they're defined and used by Rocket Chip's diplomacy package. These are shorthand operators for doing different types of binding between diplomatic nodes.

No published API documentation for this exists, but you can start poking around in the diplomacy package. The releveant location where these are defined is src/main/scala/diplomacy/Nodes.scala.

Is it good thing to use `reduce(_ ## _) ` for IndexedSeq to UInt conversion in Chisel?
How to propagate a value from a Module upwards
In FPGA, why counter with full adder raw implementation have better clock performance than infered addition '+'?
How to parametrized vector of registers in chisel
Variable sized type in Chisel
Using Chisel Submodule within another Module: Cannot assign variables to the io input
Examples in Chisel that make use of MuxCase
sbt test does not work and all the tests fail
How to export TileLink node to LazyModule's output and generate respective verilog file
Rocket Chip - Access Exception on Page Table Walk
Using subrepo for Chisel project errs
Chisel : When-otherwise clause not working in function definition
Serializer in Chisel: Register printf dont seem to make sense
chisel 5.0.0-RC1 and chiseltest
How is data width determined for load/store instructions in Rocket Core?
Implementing a diplomatic AXI Stream interface in Chisel - BundleMap.cloneType error
Exposing Simulation-only behavior in Chisel3
Is there a simple example of how to generate verilog from Chisel3 module?
Can Record class be used to create RegInit?
using rocket chip(a library of chisel) to generate a axi4crossbar in verilog language
Providing a simulation model for a chisel blackbox
Scala syntax question in Rocket-chip config.scala
Is Chisel Counter more than 32 bits possible?
Unable to get the RoCC accelerator built with the default Accumulator example for zed board
How to use the empty signal of the Queue?
How to publish Chisel package?
Where does dut in Chisel Test get defined? (About Scala syntax)
Initializing IO with a bundle in Chisel 3.5
Chisel how to test only one package
Chisel memory write mask

What is the meaning of :*= and :=* operators?

What is the meaning of := and := operators?