Hi I have the next lines of code inside a testbench module in a SystemVerilog file using Intel Quartus Prime :
`timescale 1ns/1ps
module fo;
parameter retardo_reset = 150;
parameter repetir = 2;
reg clock;
reg reset;
reg clear;
reg rden;
reg wren;
reg [7:0] data_in;
reg [7:0] data_out;
reg [7:0] queue [$:31];
reg [7:0] random_number;
wire aempty;
wire afull;
wire empty;
wire full;
// There is more code there ...
But the compiler says that in the line declaring the queue reg [7:0] queue [$:31]; there is the next error:
Error (10170): Verilog HDL syntax error at fo.sv(15) near text: "$"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Do you know what I'm doing wrong? Because that's the correct way to declare a limited queue in SystemVerilog.
According to the Quartus manual, it does not currently support synthesis of the queue data type, even when bounded.