Search code examples
chisel

assigning a signal to a non parent module

I know that in Verilog if you want to propagate a signal you have to add the signal to the ports of the module and propagate it across all the modules until you are able to connect it. I suspect that is the same for chisel but as I'm a novice...

Is it possible to connect a signal of a submodule directly to a port on a higher level module?

For instance:

Module hierarchy

top->my_peripheral->the_counter_inside_peripheral->output_my_signal top->another_peripheral->input_process_signals

my_peripheral.the_counter_inside_peripheral.output_my_signal := another_peripheral.input_process_signals
Solution

  • Chisel is the same as Verilog in this regard. In the next major version release (3.2) we will have experimental support for such synthesizable cross-module connections, but it's not yet in the published versions.

    If you build from source, you can try this out sooner by taking a look at the BoringUtils.