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vhdlverilog

VHDL equivalent of Verilog localparam

I found the following statement in a verilog modul:

localparam str2="  Display Demo  ", str2len=16;

Seems to me that str2 is a string value but I wonder how this is processed in the following code snippet. 

always@(write_base_addr)
    case (write_base_addr[8:7])//select string as [y]
    0: write_ascii_data <= 8'hff & (str1 >> ({3'b0, (str1len - 1 - write_base_addr[6:3])} << 3));//index string parameters as str[x]
    1: write_ascii_data <= 8'hff & (str2 >> ({3'b0, (str2len - 1 - write_base_addr[6:3])} << 3));
    2: write_ascii_data <= 8'hff & (str3 >> ({3'b0, (str3len - 1 - write_base_addr[6:3])} << 3));
    3: write_ascii_data <= 8'hff & (str4 >> ({3'b0, (str4len - 1 - write_base_addr[6:3])} << 3));
    endcase

Will the string value be convertet into a bit value first? Write_ascii_data is only 8 bits long, seems to me that it is too short for fully storing the end result of the case process. Is there any vhdl equivalent of localparam string ?

Solution

  • Verilog has no string types. A string literal gets converted to the equivalent ASCII bit vector, 8 bits per character. So str2 is a 128 bit vector parameter. The RHS expressions are shifting str2 to the left by some multiple of 8 bits, selecting one ASCII character.