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system-veriloghdl

assignments to unpacked array must be aggregate expressions

reg [7:0] num [0:15]={8'd64,8'd121,8'd36,8'd48,8'd25,8'd18,8'd2,8'd120,8'd0,8'd24,8'd8,8'd3,8'd35,8'd33,8'd4,8'd14};

This particular line of my code is giving the following error:

assignments to unpacked array must be aggregate expressions.

How to overcome this?

Solution

  • You need to add a ' before the leading {:

    reg [7:0] num [0:15]='{8'd64,8'd121,8'd36,8'd48,8'd25,8'd18,8'd2,8'd120,8'd0,8'd24,8'd8,8'd3,8'd35,8'd33,8'd4,8'd14};