ModelSim-Altera show error "enum literal name already exists" while Quartus not

Question

Quartus compile this code without any errors.

Code.sv

module test013_LITERAL (
    input  A,
    input  B,
    output C
);
    struct{enum{IDLE,
                SOME_STAGE_1} FSM;
             logic some_register;
            } first_machine;
    struct{enum{IDLE,
                SOME_STAGE_2} FSM;
             logic some_register;
            } second_machine;            
    assign C = A ^ B;    
endmodule

testbench.vt

  module testbench();
reg test_A;
reg test_B;
wire test_C;

test013_LITERAL DUT (.A(test_A),
                     .B(test_B),
                     .C(test_C));
initial begin    
    #100
        test_A = 0;
        test_B = 0;
    #100
        test_A = 1;
        test_B = 0;    
    #100
        test_A = 0;
        test_B = 1;        
    #100
        test_A = 1;
        test_B = 1; 
end   
endmodule

But ModelSim-Altera show error: "Enum literal name 'IDLE' already exists."

Can I write on SystemVerilog two structs in one module and then make enum in each struct with same literal ("IDLE" for example)? Is another struct means another scope?

If not can anyone describe what structs are used for?

If yes can anyone describe to me how to win ModelSim-Altera?

P.S.

Of course if there is two enums in one module and if these enums has identical members we will have an error. But I say about enums witch placed into structs.

Example:

module test013_LITERAL (
    output [3:0]first_literal,
    output [3:0]second_literal
);

struct{enum{SOME_LITERAL_0_FIRST,
            SOME_LITERAL_1_FIRST,
            IDLE,
            SOME_LITERAL_3_FIRST,
            SOME_LITERAL_4_FIRST} enum_reg;
        } first_struct;

struct{enum{SOME_LITERAL_0_SECOND,
            SOME_LITERAL_1_SECOND,
            SOME_LITERAL_2_SECOND,
            IDLE,
            SOME_LITERAL_4_SECOND} enum_reg;
        } second_struct;

assign first_literal        = first_struct.IDLE;
assign second_literal   = second_struct.IDLE;

endmodule

Result of compilling on Quartus Prime 17.1.0 (MAX-10 10M02SCE144C8G):

Info (293000): Quartus Prime Full Compilation was successful. 0 errors, 32 warnings

Result on eight LED string: 0010 0011

P.P.S.

I don't understand if struct create new scope of not.

This code compile by Quartus as well as ModelSim-Altera without any errors.

module test013_LITERAL (
    input A,
    input B,
    output C
);
    logic some_register;
    struct{logic some_register;} first_struct;
    struct{logic some_register;} second_struct;         
    assign C = A ^ B;
endmodule

Answer 1

IEEE 1800-2012, section 6.19 says:

// Correct declaration - bronze and gold are unsized
enum bit [3:0] {bronze='h3, silver, gold='h5} medal2;
// Correct declaration - bronze and gold sizes are redundant
enum bit [3:0] {bronze=4'h3, silver, gold=4'h5} medal3;

Type checking of enumerated types used in assignments, as arguments, and with operators is covered in 6.19.3. As in C, there is no overloading of literals; therefore, medal2 and medal3 cannot be defined in the same scope because they contain the same names

So, I would say that it is correct to report an error with your code because the IDLE literal appears twice.

I have tried your code on three simulators. One accepts it, the other two reject it. So, in total, three simulators reject your code, one accepts it (as does Quartus). I guess the fact that your enum is declared within a struct complicates the EDA vendors' interpretation of the standard.

The fix is to change the name of one or both (eg IDLE1 and IDLE2).