ARM Cortex-M memory access

Question

From Cortex-M0+ Devices Generic User Guide regarding memory regions-

2.2.1. Memory regions, types and attributes

Strongly-ordered:

The processor preserves transaction order relative to all other transactions.

And-

Address range: 0xE0000000- 0xE00FFFFF

Memory region: Private Peripheral Bus

Memory type: Strongly- ordered

Description: This region includes the NVIC, System timer, and System Control Block. Only word accesses can be used in this region.

Now, From CMSIS documentation-

#define __DMB()

Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

Based on the information above, it seems that in a code that accesses memory address range of 0xE0000000- 0xE00FFFFF for example, the NVIC controller and the SysTick configuration registers, I do not need to use __DMB as it is actually performed by hw.

So, for example, if we look at __NVIC_EnableIRQ-

/**
 \brief   Enable Interrupt
 \details Enables a device specific interrupt in the NVIC interrupt controller.
 \param [in]    IRQn  Device specific interrupt number.
 \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
    if ((int32_t)(IRQn) >= 0)
    {
        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
    }
}

It contains no __DMB() (and also no __DSB() nor __ISB()), so if I enable interrupt X, and then enable interrupt Y with no barrier between the operations-

NVIC_EnableIRQ(X); /* Note: __NVIC_EnableIRQ is defined as NVIC_EnableIRQ */
NVIC_EnableIRQ(Y);

Is it promised that the HW will not re-order memory accesses and will enable interrupt X before interrupt Y (lets assume that the compiler does implement function as inline)?

Answer 1

Is it promised that the HW will enable interrupt X before interrupt Y

Yes. The compiler must not optimize the write accesses or change the order - the ISER is declared volatile in CMSIS header.

Note that unlike its larger conterparts the Cortex-M0+ does not have a write buffer.