Giving inputs to error checking module from PRBS generator in verilog

Question

I have written codes for pattern generator module and error checker module in verilog. Pattern generator module generates PRBS-7. The error checker module takes sequences of two 8 bit sequences and tells me the BER( I have verified that through testbench). But i am facing trouble in giving inputs to error checker module from pattern generator module. How to do that ?

PRBS Generator Error checking Module

Answer 1

You have to make a test-bench that contains both modules and connect them up.

To generate artificial errors you have to change one or more bits in the connection between the generator and the checker:

wire [7:0] prbs_out,checker_in;
reg  [7:0] make_error;
assign checker_in = prbs_out ^ make_error;

As long as make_error is all zeros the bits pass unchanged. If you have a test loop you can occasionally make an error using the $random function:

   ... // Your major test loop
// 1 in 16 times there is an error
if (($random & 32'h0F)==0)
   make_error = 8'h01;
else
   make_error = 8'h00;

Once that is working you then can start playing with the error vector:

   // On average 1 in 16 times there is an error
   if (($random & 32'h0F)==0)
      make_error = $random & 32'h00FF; 
   else
      make_error = 8'h00;

Note that the above introduces more then one error bit which may pass undetected in some cases.