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How to give unique name to every element in a Seq of Modules in the final Verilog file

I looking for advice on how give unique name to each element of a Seq in the final generated Verilog file.

for example if I have Seq of fifos:

val fifos = Seq.fill(6)(Module(new Fifo(32, 2, true)))

in the generated Verilog I get 6 instances Fifo_0,Fif0_1,..,Fifo_5. How do I give them a unique name ?

Solution

  • You can simply suggest name each element of the Seq

    fifos(0).suggestName("FirstFifo") fifos(1).suggestName("SecondFifo")