Verilog primitives

Question

Is there any difference between these two?

1.

and(O1,input1,input2);

2.

always(O1 or input1 or input2)
           and(O1,input1,input2);

Does the primitive require an always block? Or it will be accessed whenever values of output (O1) and inputs (input1,input2) changes?

Answer 1

Do the primitive requires an always block?

No! Just like 'assign' statements they do not need an always section.

In fact if you would have tried you would have gotten a syntax error as you can not instance a module or primitive in an always section.

_{Also you there would never be a need to put the output O1 in the sensitivity list.}