What does the error "type of identifier does not agree with its usage as " " type" mean exactly in VHDL? Does port mapping affect the 'type'?

Question

I have been having issues resolving the error " type of identifier does not agree with its usage " with VHDL. As far as I understand, it means that there is something wrong when assigning values. For example, assigning std_logic to an std_logic_vector or maybe assigning an std_logic to a bit. Correct?

I get the error after i try to do port mapping.Here's where the error occurs:

LIBRARY ieee; 
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_1164.all; 
USE  IEEE.STD_LOGIC_ARITH.all;
USE  IEEE.STD_LOGIC_UNSIGNED.all;        
ENTITY ALU1 IS
 PORT (a,b,ainverse,binverse, cin:IN std_logic;
    operation: IN std_logic;
        cout, result,resolution : OUT std_logic
   );
 END ALU1;


ARCHITECTURE archAl OF ALU1 IS

COMPONENT adder
    PORT(a,b, cin: IN std_logic;
            cout,resolution: OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT(a, b :IN std_logic;
        resolution: OUT std_logic);
END COMPONENT;

COMPONENT OR1
    PORT(a, b : IN std_logic;
        resolution: OUT std_logic);
END COMPONENT;

COMPONENT mux2
 PORT( a, inverse : IN std_logic;
            resolution  :   OUT std_logic
 );
END COMPONENT;

COMPONENT XOR1
 PORT(a,b : IN std_logic;
     resolution : OUT std_logic
     );
END COMPONENT;

 --SIGNAL resolution: std_logic;



BEGIN --ARCHITECTURE BEGIN
andA:  mux2 PORT MAP(a, ainverse, resolution);
andB:  mux2 PORT MAP(b, binverse, resolution);
 resolutionAnd: AND1 PORT MAP (andA, andB, resolution);
  addA: mux2 PORT MAP(a, ainverse, resolution);
addB: mux2 PORT MAP(b, binverse, resolution);
    resolutionOr: OR1 PORT MAP (a, b, resolution);

    resolutionAdd: adder PORT MAP(ainverse, binverse, cin, cout, resolution);

resolutionXor: XOR1 PORT MAP (a,b, resolution);
PROCESS(operation, a, ainverse, resolution, b, cin,cout, BINVERSE) is
BEGIN --PROCESS BEGIN
 IF operation = "00" THEN
    result<=resolutionAnd;
 ELSIF operation = "01" THEN

    result<=resolutionOr;
 ELSIF operation = "10" THEN

     result<=resolutionAdd;

ELSIF operation ="11" THEN

     result<=resolutionAXor;
 END IF;

END PROCESS;
END archAl;

The error occurs in resolutionAnd: AND1 PORT MAP (andA, andB, resolution);

I get Error (10476): VHDL error at alu.vhd(158): type of identifier "andA" does not agree with its usage as "std_logic" type and Error (10476): VHDL error at alu.vhd(158): type of identifier "andB" does not agree with its usage as "std_logic" type . So, the logical thing to do it to search mux2 which affect andA, andB to see if there is an inconsistency between the assigned types.

The code for mux2 is :

ENTITY mux2 IS
PORT(a, inverse: IN std_logic;
   resolution       :   OUT std_logic);
END mux2;

ARCHITECTURE archMux2 OF mux2 IS
  BEGIN
     PROCESS(a, inverse)
     BEGIN
         IF inverse = '0' THEN
            resolution <= a;
         ELSE
            resolution <= NOT a;
        END IF;
     END PROCESS;
 END archMux2;

I cannot detect any inconsistency in the assigned types. So I suppose I have not understood the error correctly or something wrong is happening and I am not aware of it. Can someone assist please?

Answer 1

andA and andB are labels:

andA:  mux2 PORT MAP(a, ainverse, resolution);
andB:  mux2 PORT MAP(b, binverse, resolution);
^^^^

You seem to have connected them to them ports of the AND component resolutionAnd:

resolutionAnd: AND1 PORT MAP (andA, andB, resolution);
                              ^^^^  ^^^^