Verilog: Assigning a localparam to a bit vector wire

Question

I have the following Verilog code snippet:

module (...)
input wire [7:0] sw;
output wire [6:0] LED4;
output wire [6:0] LED3;
output wire [6:0] LED2;
output wire [6:0] LED1;
localparam charA = 7'b1110111;
localparam charB = 7'b0011111;
localparam charC = 7'b1001110;
localparam charD = 7'b0111101;

always @ (sw)
begin
    if (sw[7] == 1'b1)
    begin
      LED4 = charA;
      LED3 = charB;
      LED2 = charC;
      LED1 = charD;
    end
end
endmodule

On using ISPLever to compile, an error is thrown:

Assignment target LED4 must be of type reg or genvar
Assignment target LED3 must be of type reg or genvar
Assignment target LED2 must be of type reg or genvar
Assignment target LED1 must be of type reg or genvar

I am not allowed to change the type of the variables. What other way can I use to assign local parameters to the bit vector wires?

Answer 1

I find the constraint that you are not allowed to change the type of the variables very weird. Making them 'output reg[6:0] ...' would get rid of your errors and this would have no effect of any other part of the circuit. e.g. the code that calls your module does not care if it is a wire or reg.

But!
Even with using 'reg' your code is still wrong as you are making latches. The always(sw) is combinatorial and you should put a 'else' section in there.

To work with wires you can then use:

assign LED4 = sw[7] ? charA : <your else code>; 
assign LED3 = sw[7] ? charB : <your else code>; 
assign LED2 = sw[7] ? charC : <your else code>; 
assign LED1 = sw[7] ? charD : <your else code>;