Verilog case statement returning incorrect values

Question

I'm supposed to write a simple CU using a case statement but the output isn't matching what I specified in the case statement. I figure I'm making some kind of fundamental mistake here but I can't figure out what it is.

This is my module:

`timescale 1ns / 1ps

module ControlUnit(Opcode,   RegDst, Jump,     Branch, MemRead, 
                   MemtoReg, ALUOp,  MemWrite, ALUSrc, RegWrite);

   /* IO */
   // Inputs
   input  [5:0] Opcode;
   // Outputs
   output [1:0] ALUOp;
   output       RegDst;
   output       Jump;
   output       Branch;
   output       MemRead;
   output       MemtoReg;
   output       MemWrite;
   output       ALUSrc;
   output       RegWrite;

   // Hold output value from case statement.
   reg [9:0] out;

   // Assign outputs based on Opcode recieved. 
   always@( * ) begin
      case( Opcode )
      // out format:
      // RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Jump,ALUOp
         6'b00_0000 : out = 1_0_0_1_0_0_0_0_10 ; // R-Type
         6'b10_0011 : out = 0_1_1_1_1_0_0_0_00 ; // lw
         6'b10_1011 : out = 0_1_0_0_0_1_0_0_00 ; // sw
         6'b00_0100 : out = 0_0_0_0_0_0_1_0_01 ; // beq
         6'b00_0010 : out = 0_0_0_0_0_0_0_1_00 ; // j
         default    : out = 0_0_0_0_0_0_0_0_00 ; // Default case. 
      endcase
   end

   // Assign outputs according to result from case statement.   
   assign { RegDst,  ALUSrc,   MemtoReg, RegWrite, 
            MemRead, MemWrite, Branch,   Jump, 
            ALUOp } = out;

endmodule

And here are the outputs I'm getting:

Opcode : out

00_0000 : 0001001010

10_0011 : 0001100000

10_1011 : 0000010000

00_0100 : 1111101001

00_0010 : 0001100100

None of them match any of the cases. For my test bench I'm just using what Xilinx generated plus the following:

    initial begin
      // Initialize Inputs
      Opcode = 0;

      // Add stimulus here
      Opcode = 6'b00_0000;
      #100
      Opcode = 6'b10_0011;
      #100
      Opcode = 6'b10_1011;
      #100
      Opcode = 6'b00_0100;
      #100
      Opcode = 6'b00_0010;
      #100
      Opcode = 6'b00_0010;

    end

One of the constraints of the assignment is that we aren't supposed to implement a state machine and have to use this exact port list, hence the case statement. I've also seen online that this could be done with a chain of assign statements but the teacher said it can be done with a case statement so I'm trying to figure that out.

Answer 1

You forgot to add 10'b in front of out assignment. It should be
out = 10'b1001000010.
Else it will take it as an integer value in decimal format (not binary format).