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setverilogbitquartus

Quartus 2 verliog using curly craces to set particular bits

Hi I am new to verilog and I try to set some particular bits from one reg variable to another reg but it didn't work for me. what am ı doing wrong? 

reg [31:0] a;
reg [31:0] b;

initial begin
 a =32'b0;
 b =32'b1;
 $display("current value of a = %32b ",a);
 a ={b[5:0]};
 $display("value of a %32b ",a);
 #10 $finish;
 end

bit of a from a[0] to a[5] should be 1 but only a[0] became 1

Solution

  • In you code b = 32'b1 yields {31{1'b0},1'b1}, so only b[0] is equal to one.

    In SystemVerilog (check: IEEE1800-2012, 5.7.1 Integer literal constants) you can use automatic left padding of constant literal numbers using a single-bit value, i.e. b = '1 to set all bits of b to one.

    Using Verilog, simply assign another value to b (i.e. b = 32'b11111) or change your code to following:

    a[4:0] = {5{b[0]}}