Verilog using @ with conditional if

Question

Hello I have a question about Verilog grammar.

I am aware that @ is used with always usually.

but I want to do some action when a variable changes its value.

for example, I want to find out if switch is changing.

So, I tried if (@ posedge switch or negedge switch)

But this made an error.

Is there any other way to do this?

Thanks in advance

Answer 1

If you want to write a synchronous design (And you want to do that ;), you have to change state of all your signal on one clock edge (generally rising).

Then to detect switch edge you have to save state of switch value and compare it with actual on rising edge of clock.

always @(posedge clock)
   begin

       if (switch_old != switch)
             switch_edge <= 1'b1;
       else
             switch_edge <= 1'b0;

       switch_old  <= switch;
   end

You can't do what you ask in a synchronous design, then it can't be syntesizable reasonably.