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Verilog: Changing multiple states in one case statement

Basically I'm trying to display the sum or product of two numbers (inputted using switches on an FPGA) onto a 7-segment display. I know that both my addition and multiplication bits work fine, as I've tested them separately.

I'm having trouble with the LSB though. No matter what it just defaults to F and never changes. I think Verilog doesn't allow me to modify both Cout1 and Cout0 in the same case statement. Is there a workaround for this? See my code, below.

always@*
    if (key1press)
    casex(PrintSum)

        // Hex 1 (MSB)
        // Works!
        5'b0xxxx : Cout1 = 7'b1000000;  //0 if S[4] = 0
        5'b1xxxx : Cout1 = 7'b1111001;  //1 if S[4] = 1

        // Hex 0 (LSB)
        // Doesn't work :(
        5'bx0000 : Cout0 = 7'b1000000;  //0
        ...
        5'bx1111 : Cout0 = 7'b0001110;  //F
        //default  : begin
        //            Cout1 = 7'b1000000;   //0 by default
        //            Cout0 = 7'b1000000;   //0 by default
        //end
    endcase

Thanks in advance everyone :)

Solution

  • In simulations, case statements will execute first match. Everything will match the first two conditions (5'b0xxxx, 5'b1xxxx). If you move these conditions to the end, then they will never be reached as there will be a match in the 5'bx0000 to 5'bx1111 range.

    There isn't overlap between the care bits. Therefore, the simplest solution is to split Cout1 and Cout0 into separate constitutional statements:

    begin
  if (PrintSum[4]) begin
    Cout1 = 7'b1111001;  //1 if S[4] = 1
  end
  else begin
    Cout1 = 7'b1000000;  //0 if S[4] = 0
  end

  case(PrintSum[3:0])
    4'b0000 : Cout0 = 7'b1000000;  //0
    // ...
    4'b1111 : Cout0 = 7'b0001110;  //F
  endcase
end

    Other things to be aware of: