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veriloghdl

Getting Z and X at output for a basic Full Adder

I have been designing a basic full adder with two half adder modules and trying to test it with a testbench. There are no compile errors, but at the output (Waveform), I get Z and X for Sum and Carry. I am stuck and not sure what next to look at to correct this error.

Any advice in what next steps (or some pointers) to be checked in order to rectify this would be helpful.

Here is the Verilog code for the Full Adder:

module half_adder(x,y,S,C);
input x,y;
output S,C;

xor G1(S,x,y);
and G2(C,x,y);

endmodule

module full_adder(x,y,z,S,C);
input x,y,z;
output S,C;
wire S1,C1,C2;

half_adder HA1(S1,C1,x,y);
half_adder HA2(S,C2,S1,z);
or G3(C,C1,C2);

endmodule

Testbench for the above:

module tb_fulladder;
wire S,C;
reg x,y,z;

full_adder DUT(x,y,z,S,C);

initial
begin
x=1'b0;y=1'b0;z=1'b0;
#50
x=1'b0;y=1'b0;z=1'b1;
#50
x=1'b0;y=1'b1;z=1'b0;
#50
x=1'b0;y=1'b1;z=1'b1;
#50
x=1'b1;y=1'b0;z=1'b0;
#50
x=1'b1;y=1'b0;z=1'b1;
#50
x=1'b1;y=1'b1;z=1'b0;
#50
x=1'b1;y=1'b1;z=1'b1;
end

initial
#500
$finish;

endmodule

Here is the waveform:

enter image description here

Solution

  • You made a mistake in your connections to half_adder. You need to change the order of the port signals. Change:

    half_adder HA1(S1,C1,x,y);
half_adder HA2(S,C2,S1,z);

    to:

    half_adder HA1 (x,y,S1,C1);
half_adder HA2 (S1,z,S,C2);

    I discovered this by looking at the waveforms for the internal full and half adder signals.

    This is why it is better to use connection-by-name instead of connection-by-position. For example, use:

    half_adder HA1 (.x(x), .y(y), .S(S1), .C(C1));

    Using this syntax, the port order does not matter. Refer to the free IEEE Std 1800-2012, 23.3.2 Module instantiation syntax.