I have created a design and would like to compile the design in order to create a binary file for the CPLD. However when I try to compile the design, it outputs a warning saying that the timing requirements not met. It seems like it is complaining about the following VHDL component where the external clock is divided into a lower clock frequency that is used by the other VHDL components in the design:
entity clk_divider is
generic (COUNTER_MAX : integer := 256000);
port(
clk_in : in std_logic;
reset : in std_logic;
clk_out : out std_logic
);
end clk_divider;
architecture Behavioral of clk_divider is
signal signal_level : std_logic := '0';
signal counter : integer range 0 to COUNTER_MAX := 0;
begin
clk_divider : process (clk_in, reset)
begin
if (reset = '1') then
signal_level <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = COUNTER_MAX) then
signal_level <= not(signal_level);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= signal_level;
end Behavioral;
The critical warning message shown during design compilation is shown below:
Critical Warning (332012): Synopsys Design Constraints File file not found: 'monitor.sdc'.
A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints.
Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name clk clk
Info (332105): create_clock -period 1.000 -name clk_divider:clk_module|signal_level clk_divider:clk_module|signal_level
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -7.891
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -7.891 -123.541 clk
Info (332119): -1.602 -5.110 clk_divider:clk_module|signal_level
Info (332146): Worst-case hold slack is -0.816
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -0.816 -0.816 clk
Info (332119): 1.732 0.000 clk_divider:clk_module|signal_level
Info (332146): Worst-case recovery slack is -4.190
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -4.190 -20.950 clk_divider:clk_module|signal_level
Info (332119): -3.654 -76.734 clk
Info (332146): Worst-case removal slack is 4.320
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 4.320 0.000 clk
Info (332119): 4.856 0.000 clk_divider:clk_module|signal_level
Info (332146): Worst-case minimum pulse width slack is -2.289
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.289 -2.289 clk
Info (332119): 0.247 0.000 clk_divider:clk_module|signal_level
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
What is the reason for this warning message and how can I solve it? Also what does the slack numbers say about my design?
Since monitor.sdc cannot be found, Quartus tries to synthesize your circuit at 1GHz (period=1ns) as far as the logs reveal the following constraints.
create_clock -period 1.000 -name clk clk
create_clock -period 1.000 -name clk_divider:clk_module|signal_level clk_divider:clk_module|signal_level
The first line is for clk port (it must be in the top-level module/entity) and the second line is for signal_level signal. You can modify the periods appropriately and put the constraints into monitor.sdc. Then you should add that file to the project.
A slack value tells you the difference between the target and the actual. If a path meets the timing requirement, it has a positive slack. If doesn't meet, the slack is negative.
Your target clock period was 1ns, but you got -7.891ns slack for the critical (worst) path. The actual period achievable can be calculated as follows.
actual period = target period - setup slack = 1.000 - (-7.891) = 8.891ns
According to the results above, 8.9ns can be an achievable period for clk. I would also try smaller values, but there is no need if your real input clock (clk) is not faster than 100MHz.
The period of signal_level depends on the minimum value of COUNTER_MAX. Actually the rest of the circuit already seems faster than clk_divider module, because the slack (-1.602) of signal_level is better. You can set the same period with clk.