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verilogsystem-verilog

What does '1 mean in verilog?

I have a register with 4bits.

 reg[3:0] a;

And I want to assign a single bit to it like

 a <= '1;

Apparently it is not the same 1'b1 and 1. I am new to verilog and not sure about its syntax. Can anyone enlighten me please.

Solution

  • This sets all bits to 1, I believe.