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logicveriloghdl

Verilog gate definition difference

This is two type half adder definition on Verilog.

Is there a difference between them? Which should I choose? Why?

halfAdder1

xor(s,x1,x2);
and(c,x1,x2);

halfAdder2

assign s=x1^x2;
assign c=x1&x2;
Solution

  • First one is known as structural model, using the gate-level primitives. Second one is known as RTL model (Register Transfer Level). Both models are fully synthesizable and likely to generate the exact same hardware.

    Said that, the RTL modelling is a bit closer to the higher-level programming languages and thus more readable for humans. In addition it is abstracting the gates to the arithmetical/logical operators, giving the synthesis tool more flexibility to choose the appropriate gates.

    On the other hand the gate level is more appropriate if you have a schematic of your circuit and want to directly translate it into HDL.