How to use default modules like M2_1 MUX or FD flipflop in xilinx verilog?

Question

I am able to use these default modules in xilinx schematic like M2_1 MUX, FD flipflop etc.

In verilog I can able to use only elementary gates like and, or ,not,xor etc.

But can I use these built-in Multiplexer (M2_1) or Flipflop(FD) in verilog?, because if I use behavioral code, there may be poor synthesis in synopsis or xilinx for some cases. Also I want to use system level design.

Please help me to solve this issue. Do I need to include any library to access this(built-in gates)?

Please provide me example codes. I want direct instantiation of these(Mux and Flipflop) in verilog just as and, or etc.

Answer 1

Yes you can use them in verilog. Xilinx provides user guides for how to do it (example for 7 series here)

The user guide that I've given link to provides an example for FDCE flip flop such as (page 131):

// FDCE:Single Data Rate D Flip-Flop with Asynchronous Clear and
// Clock Enable (posedge clk).
// 7 Series
// Xilinx HDL Libraries Guide, version 2012.2 
FDCE #(
    .INIT(1'b0)
    // Initial value of register (1'b0 or 1'b1)
)
FDCE_inst
(
    .Q(Q),
    // 1-bit Data output
    .C(C),
    // 1-bit Clock input
    .CE(CE),
    // 1-bit Clock enable input
    .CLR(CLR),
    // 1-bit Asynchronous clear input
    .D(D)
    // 1-bit Data input 
);
// End of FDCE_inst instantiation